Agnisys Training Schedule 2012
Following is the tentative schedule for classes in various cities. Please contact This e-mail address is being protected from spambots. You need JavaScript enabled to view it for registration and more details.
| Class | Days | Jan | Feb | Mar | Apr | May | June |
|---|---|---|---|---|---|---|---|
| SystemVerilog Courses | |||||||
| Introduction to Universal Verification Methodology (UVM) (#UVM01) |
4 | Chennai | B'lore | ||||
| Introduction to the Open Verification Methodology (OVM) (#OVM01) | 4 | Puna | |||||
| SystemVerilog for Verification (#SVV01) | 4 | Delhi/NCR | B'lore | Delhi/NCR | |||
| Advanced Open Verification Methodology (OVM) (#OVM02) | 3 | ||||||
| Advanced Universal Verification Methodology (UVM) (#UVM02) | 2 | ||||||
| SystemVerilog Assertions (SVA) (#SVA01) | 1 | Delhi/NCR | B'lore | Delhi/NCR | |||
| SystemC Courses | |||||||
| SystemC Modeling with Introduction to TLM 2.0 (#SC-TLM02) | 3 | B'lore | B'lore | Delhi/NCR | |||
| SystemC Modeling with TLM 2.0 (#SC-TLM01) | 4 | ||||||
| TLM 2.0 (#TLM01) | 2 | ||||||
| Introduction to SystemC for Verification (#SCV01) | 3 | Delhi/NCR | |||||
| Advanced SystemC Verification (#SCV02) | 3 | ||||||
| Introduction to C++ (#CPP02) | 2 | B'lore | B'lore | Delhi/NCR | |||
| Other HDL Courses | |||||||
| Introduction to Verilog for RTL Design (#VER01) | 3 | ||||||
| Introduction to VHDL for RTL Design (#VHD01) | 4 | ||||||
| Advanced VHDL (#VHD02) | 3 | ||||||
