IVerifySpec^TM : Closed Loop Requirement Verification

IVerifySpec^TM is a SOC/FPGA Verification process management tool. It enables the Management and Design Team to know where they are at in the verification process. It integrates design requirements, verification plan and the results from the simulation environment all in a centralized place. Read more about this methodology on Mentor Graphics website.

IDesignSpec^TM and IVerifySpec^TM enable design teams to raise their productivity and achieve better quality.

Key Features

1. Centralized data management
2. Maintains links to the Design requirements thru the Verification process
3. Easy to learn, ready-to-go out-of-the-box
4. Does not impact your current process.

Key Benefits

1. Requirement tracing thru the design and verification process
2. Understand the impact of Verification shortcomings on the entire product
3. Monitor the verification progress from a centralized place
4. Close the loop from requirements thru implementation to verification

Need to know more?

Read the article about Closed Loop Requirement Verification in the partner's corner of the Mentor Graphics's Verification Horizon Newsletter (page 36 onwards).

For a short web based demo please contact: